1. Field of the Invention
The present invention relates generally to methods for fabricating field effect transistor (FET) devices. More particularly, the present invention relates to methods for fabricating, with enhanced performance, field effect transistor (FET) devices.
2. Description of the Related Art
Semiconductor integrated circuit microelectronic fabrications are formed from semiconductor substrates within and upon which are formed semiconductor devices and over which are formed patterned conductor layers which are separated by dielectric layers.
Common in the art of semiconductor integrated circuit microelectronic fabrication for use when fabricating semiconductor integrated circuit microelectronic fabrications are field effect transistor (FET) devices. Field effect transistor (FET) devices are common in the art of semiconductor integrated circuit microelectronic fabrication as switching devices within both semiconductor integrated circuit microelectronic memory fabrications and semiconductor integrated circuit microelectronic logic fabrications.
While field effect transistor (FET) devices are thus common in the art of semiconductor integrated circuit microelectronic fabrication and often essential in the art of semiconductor integrated circuit microelectronic fabrication, field effect transistor (FET) devices are nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication. In that regard, and as semiconductor integrated circuit microelectronic fabrication integration levels have increased and semiconductor device dimensions have decreased, it has become increasingly more difficult in the art of semiconductor integrated circuit microelectronic fabrication to fabricate within semiconductor integrated circuit microelectronic fabrications field effect transistor (FET) devices with enhanced performance.
It is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication to fabricate within semiconductor integrated circuit microelectronic fabrications field effect transistor (FET) devices with enhanced performance.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of semiconductor integrated circuit microelectronic fabrication for fabricating within semiconductor integrated circuit microelectronic fabrications field effect transistor (FET) devices with desirable properties.
Included among the methods, but not limiting among the methods, are methods disclosed within: (1) Hiroki et al., in U.S. Pat. No. 5,830,788 (a method for fabricating a field effect transistor (FET) device with enhanced performance by fabricating the field effect transistor (FET) device with an asymmetric channel region); (2) Hsu et al., in U.S. Pat. No. 5,891,782 (a method for fabricating a field effect transistor (FET) device with enhanced performance by fabricating the field effect transistor (FET) device with an asymmetric channel region of width narrower than a gate electrode formed thereover); (3) Jiang et al., in U.S. Pat. No. 5,925,914 (a method for fabricating a field effect transistor (FET) device with enhanced performance by fabricating the field effect transistor (FET) device with asymmetric source/drain regions); (4) Krivokapic, in U.S. Pat. No. 5,960,291 (another method for fabricating a field effect transistor (FET) device with enhanced performance by fabricating the field effect transistor (FET) device with an asymmetric channel region); (5) Gardner et al., in U.S. Pat. No. 6,146,934 (another method for fabricating a field effect transistor (FET) device with enhanced performance by fabricating the field effect transistor (FET) device with asymmetric source/drain regions); and (6) Xiang et al., in U.S. Pat. No. 6,168,999 (a method for fabricating a field effect transistor (FET) device with enhanced performance by fabricating the field effect transistor (FET) device with both an asymmetric channel region and asymmetric source/drain regions).
The disclosures of each of the foregoing references are incorporated herein fully by reference.
Desirable in the art of semiconductor integrated circuit microelectronic fabrication are additional methods and materials which may be employed for fabricating within semiconductor integrated circuit microelectronic fabrications field effect transistor (FET) devices with enhanced performance.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a a method for fabricating a field effect transistor (FET) device.
A second object of the present invention is to provide the method for fabricating the field effect transistor (FET) device in accord with the first object of the present invention, wherein the field effect transistor (FET) device is fabricated with enhanced performance.
A third object of the present invention is to provide the method for fabricating the field effect transistor (FET) device in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a field effect transistor (FET) device.
To practice the method of the present invention, there is first provided a semiconductor substrate of a first polarity. There is then formed over the semiconductor substrate a gate electrode such as to define within the semiconductor substrate a source region separated from a drain region by a channel region defined beneath the gate electrode. There is then formed simultaneously within the semiconductor substrate a first source extension region within the source region, separated from a first drain extension region within the drain region, each of the foregoing first extension regions being of a second polarity opposite the first polarity. There is also formed simultaneously within the semiconductor substrate a first source side pocket implant region within the channel region adjoining the source region, separated from a first drain side pocket implant region within the channel region adjoining the drain region, each of the foregoing first pocket implant regions being of the first polarity. There is also formed within the semiconductor substrate a second source extension region of the second polarity formed at a location such as to at least in part overlap the first source extension region, but not a second drain extension region of the second polarity formed at a location such as to at least in part overlap the first drain extension region. Finally, there is also formed within the semiconductor substrate a second source side pocket implant region of the first polarity formed at a location such as to at least in part overlap the first source side pocket implant region, but not a second drain side pocket implant region formed at a location such as to at least in part overlap the first drain side pocket implant region.
The present invention provides a method for fabricating a field effect transistor (FET) device, wherein the field effect transistor (FET) device is fabricated with enhanced performance.
The present invention realizes the foregoing object by fabricating the field effect transistor (FET) device with both: (1) a source region asymmetrically doped with respect to a drain region; and (2) an asymmetrically doped channel region.
The method of the present is readily commercially implemented.
The present invention employs methods and materials as are generally conventional in the art of semiconductor integrated circuit microelectronic fabrication, but employed within the context of specific process limitations which provide, at least in part, the present invention. Since it is thus at least in part specific process limitations which provide the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.